(a) Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device using a dual-damascene pattern.
(b) Description of the Related Art
With the increase in a degree of integration of a semiconductor integrated circuit, the number of interconnections required to connect elements to each other is also being increased. Accordingly, methods employing two or more metal layers are commonly used for manufacturing such integrated circuits. When the degree of integration of an integrated circuit is increased, it is not easy to achieve high production yield and high reliability.
A semiconductor device manufacture method using a damascene process is a manufacture technique including a step of forming interconnection lines by means of a first etching for forming trenches on a flat dielectric film, and filling the trenches with metal. Through this method, a semiconductor substrate can be filled with copper, which is not easily etched. This method using the damascene process is a method employed most commonly in a subquarter micron interconnection manufacture industry.
Recently, with the increase of the degree of integration of the semiconductor device, a multi-metal interconnection structure has been required. The damascene process has been proposed to form multi-metal interconnections efficiently, and particularly, a dual-damascene process is being employed for this process.
This dual-damascene process is used to form bit lines or word lines in addition to metal interconnections. Particularly, for the multi-metal interconnections, this process can form via holes for contacting an upper layer metal interconnection with a lower layer metal interconnection at once. Moreover, this process can remove steps generated when the metal interconnections are formed, thereby facilitating subsequent processes.
The dual-damascene process is generally classified into a via first method and a trench first method. The via first method is a method for first etching an insulation film using a lithography process to form via holes, and then forming trenches on the via holes by etching the insulation films again.
On the contrary, the trench first method is a method for first forming the trenches, and then forming the via holes. Of the two methods, the via first method is more commonly employed.
Furthermore, since a metal film such as aluminum (Al) of the multi-metal interconnections in the manufacture process of the semiconductor device has a very high surface reflectivity, there may arise a problem of notching and thinning of a metal film due to light scattering generated during a lithography process for patterning the metal film.
This problem becomes more serious as the width of the metal interconnection is decreased with the increase of integration of the semiconductor device. In order to avoid this problem, an antireflective coating (ARC) film is formed on the metal film.
On the other hand, with the miniaturization of a design rule below 0.15 μm, it becomes difficult to form via hole patterns and metal interconnection patterns in a backend process of aluminum. Although aluminum has a low specific resistance and a good conductivity, it has a disadvantage in that it has a weak resistance to electron-migration (EM) forming voids due to a mass transport. Accordingly, copper, which has a strong resistance to EM over aluminum, is considered as a next generation interconnection material.
The dual-damascene process is employed to form the metal interconnections of the semiconductor integrated circuit using copper. However, in conventional dual-damascene processes, since a damascene profile has a nearly right angle, it is not easy to remove the ARC film in a subsequent lithography process, thereby difficulty is encountered in manufacture of the semiconductor device.